1. Field of the Invention
This invention relates to semiconductor integrated circuit memory devices, and more particularly to devices implementing static random access memory (SRAM) cells having load transistors.
2. Related Art
FIG. 1 is a schematic drawing of a conventional memory circuit 100 that includes six-transistor (6T) static random access memory (SRAM) cell 101 fabricated using cross-connected complementary metal oxide semiconductor (CMOS) inverters. SRAM cell 101 includes N-type MOS (NMOS) transistors N1, N2, N3, and N4, and P-type MOS (PMOS) transistors P1 and P2, which are connected as illustrated. Transistors P1 and N1 are coupled to form inverter 110, and transistors P2 and N2 are coupled to form inverter 111. These inverters 110-111 are cross-coupled, thereby forming a latch circuit that stores a data bit. As described below, the stability of this latch circuit can be improved by making PMOS transistors P1 and P2 weaker.
Although only a single SRAM cell 101 is illustrated in FIG. 1, it is understood that many SRAM cells identical to SRAM cell 101 are typically configured in an array. The transistors located in the SRAM cells of such a memory array are hereinafter referred to as “memory” transistors. Thus, SRAM cell 101 includes PMOS memory transistors P1-P2 and NMOS memory transistors N1-N4.
Memory circuit 100 also includes control circuit 102, sensing circuit 103, comlementary bit lines 120-121 and word line 122, which are coupled to SRAM cell 101 as illustrated. The operation of control circuit 102 and 103 are well known to those of ordinary skill in the art. Control circuit 102 and sensing circuit 103 typically contain both NMOS and PMOS transistors in a variety of conventional configurations. These transistors, and other transistors located outside of the memory array, are hereinafter referred to as “peripheral” transistors.
Stability is defined as the ability of a memory cell to retain its programmed state. SRAM cell stability is therefore desirable. However, as SRAM cells become smaller, and the SRAM cell operating voltages are reduced to 2.5 Volts and lower, it can become difficult to maintain SRAM cell stability. The stability of 6T SRAM cell 101 can be enhanced by reducing the drain-source current (IDS) in the pull-up PMOS memory transistors P1 and P2 when these transistors are in a conductive state. Reducing the drain-source current IDS in PMOS memory transistors P1 and P2 will also reduce the power consumption of the associated memory array. One method of reducing the current IDS is to make PMOS transistors P1 and P2 “weaker” (or less conductive). While weaker transistors switch relatively slowly, PMOS memory transistors P1-P2 are used as load transistors, such that the speed of these transistors does not adversely affect the speed of SRAM cell 101.
One way of making a PMOS transistor weaker is to lightly dope the source and/or drain regions of the PMOS transistor. Another way of making a PMOS transistor weaker in a dual-gate process is to fabricate the PMOS transistor with an N+ type gate electrode. A PMOS transistor having an N+ type gate will have a higher threshold voltage (VT) and a lower drain-source current (IDS) than a similar PMOS transistor having a P+ type gate.
While it is desirable for PMOS memory transistors to be weak, it is generally undesirable for PMOS peripheral transistors to be weak, because weak PMOS peripheral transistors will decrease the operating speed of the peripheral circuitry (e.g., control circuit 102 and sensing circuit 103). Thus, some memory circuits use PMOS peripheral transistors having P+ type gates, because the lower threshold voltage (VT) and higher drain-source current (IDS) of such PMOS transistors increases operating speed.
FIG. 2 is a simplified cross-sectional view showing a conventional CMOS structure 200 that includes relatively weak PMOS memory transistor P1, NMOS memory transistor N1, relatively strong PMOS peripheral transistor P11 and NMOS peripheral transistor N11. CMOS structure 200 includes semiconductor substrate 201, P-wells 202-203, N-wells PMOS 204-205, field oxide regions 206-207, gate oxide layer 208, P− type lightly doped drain/source (LDD) regions 209, heavily doped P+ drain/source regions 210, N− type LDD regions 211, heavily doped N+ drain/source regions 212, P+ type gate electrode 220, N+ type gate electrodes 221-223, and sidewall spacers 225.
PMOS memory transistor P1 is a relatively weak transistor in view of N+ type gate electrode 223, P− type LDD regions 209, and the absence of heavily doped P+ drain/source regions 210. PMOS peripheral transistor P11 is a relatively strong transistor in view of P+ gate electrode 220, P− type LDD regions 209, and P+ type drain/source regions 210. The P− type LDD regions 209 of PMOS transistors P1 and P11 are formed at the same time, and therefore have the same dopant concentration. Because PMOS transistor P11 is a surface channel device, this transistor requires a relatively high P− LDD dose in order to achieve an acceptable current driving capability (IDS). Because PMOS transistor P1 receives the same relatively high P− LDD dose, PMOS transistor P1 may exhibit an undesirably high current driving capability (IDS), thereby deteriorating cell stability, and possibly necessitating a larger cell size to make the cell more stable. CMOS structure 200 is described in more detail in U.S. Pat. No. 6,191,460.
Although CMOS structure 200 demonstrates lowered current IDS and improved stability with respect to previously known 6T SRAM memory circuits, it would be desirable to have a CMOS structure that further reduces the current driving capability (IDS) and enhances memory cell stability. It would also be desirable if such a CMOS structure could be fabricated without significantly modifying the standard CMOS process flow.